Tauākī Tūmataitinga: He mea tino nui to maatauranga ki a matou. He kupu nui to maatau kamupene kia kaua e whakaatu i o korero whaiaro ki tetahi atu whakaaetanga.
Tauira No.: NSO4GU3AB
Nga waka: Ocean,Air,Express,Land
Momo utu: L/C,T/T,D/A
Kupu Whakauru: FOB,EXW,CIF
4GB 1600mHz 240-Pin DDR3 Udimm
Te hōmu hōmu
Revision No. |
History |
Draft Date |
Remark |
1.0 |
Initial Release |
Apr. 2022 |
|
Te tono i te tepu korero
Model |
Density |
Speed |
Organization |
Component Composition |
NS04GU3AB |
4GB |
1600MHz |
512Mx64bit |
DDR3 256Mx8 *16 |
Whakaaturanga
Ko te Hengstar Conberffed DDR3 DDR3 DDR3 SDRAM (kaore i te whakarereke i nga waahanga mahara-tau takirua) he mana iti, he kaupapa whakamahara mahi tere-tere e whakamahi ana i nga taputapu DDR3. NS04gu3AB ko te 512m x 64-bit e rua Rua 4GB DDR3-1600 CL11 1.5v SDRAM i te hua dimm, e pa ana ki nga waahanga tekau ma ono. Ko te SPD e whakamaherehia ana ki a Jedec Latecy Latency DDR3-1600 Timing o 11-11-11 i 1.5V. Ia 240-Pin Dimm te whakamahi i nga maihao whakapā koura. Ko te SDRAM kaore e kitea hei whakamahi ma te mahara ki te whakauru i roto i nga punaha penei i te PC me nga mahi mahi.
Ngakau
power supply: VDD = 1.5v (1.425v ki te 1.575v)
vddq = 1.5v (1.425v ki te 1.575v)
800mhz Fck mo te 1600MB / Sec / Pin
8 Bank Motuhake Motuhake
programable Cas Lateny: 11, 10, 9, 8, 7, 6
programbab Tāpiri Tāpiri: 0, CL - 2, CL - 1 karaka ranei
8-bit mua-fetch
burst Te roa:
bi-ahunga atu i te Strobe Raraunga Whakawhitiwhiti
inernal (whaiaro); Ko te whakapae a-roto ma te ZQ Pin (RZQ: 240 OHM ± 1%)
Ko te whakamutu i te whakamutu ma te whakamahi i te titi odt
° C, 3.9us i te 85 ° C <tcase <95 ° C
asynnnchronous te tautuhi
ADJJEBLED DINGP-putanga puku
fly - na te whakaaro nui
pcb: Te teitei 1.18 "(30mm)
rohs Whakarite me Halogen-Free
Ko nga tohu matua matua
MT/s |
tRCD(ns) |
tRP(ns) |
tRC(ns) |
CL-tRCD-tRP |
DDR3-1600 |
13.125 |
13.125 |
48.125 |
2011/11/11 |
Te ripanga wāhitau
Configuration |
Refresh count |
Row address |
Device bank address |
Device configuration |
Column Address |
Module rank address |
4GB |
8K |
32K A[14:0] |
8 BA[2:0] |
2Gb (256 Meg x 8) |
1K A[9:0] |
2 S#[1:0] |
Whakaahuatanga PIN
Symbol |
Type |
Description |
Ax |
Input |
Address inputs: Provide the row address for ACTIVE commands, and the column |
BAx |
Input |
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or |
CKx, |
Input |
Clock: Differential clock inputs. All control, command, and address input signals are |
CKEx |
Input |
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry |
DMx |
Input |
Data mask (x8 devices only): DM is an input mask signal for write data. Input data is |
ODTx |
Input |
On-die termination: Enables (registered HIGH) and disables (registered LOW) |
Par_In |
Input |
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. |
RAS#, |
Input |
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being |
RESET# |
Input |
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and |
Sx# |
Input |
Chip select: Enables (registered LOW) and disables (registered HIGH) the command |
SAx |
Input |
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address |
SCL |
Input |
Serial |
CBx |
I/O |
Check bits: Used for system error detection and correction. |
DQx |
I/O |
Data input/output: Bidirectional data bus. |
DQSx, |
I/O |
Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; |
SDA |
I/O |
Serial |
TDQSx, |
Output |
Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD |
Err_Out# |
Output (open |
Parity error output: Parity error found on the command and address bus. |
EVENT# |
Output (open |
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical |
VDD |
Supply |
Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The |
VDDSPD |
Supply |
Temperature sensor/SPD EEPROM power supply: 3.0–3.6V. |
VREFCA |
Supply |
Reference voltage: Control, command, and address VDD/2. |
VREFDQ |
Supply |
Reference voltage: DQ, DM VDD/2. |
VSS |
Supply |
Ground. |
VTT |
Supply |
Termination voltage: Used for control, command, and address VDD/2. |
NC |
– |
No connect: These pins are not connected on the module. |
NF |
– |
No function: These pins are connected within the module, but provide no functionality. |
Nga tuhinga : Ko te tepu Whakaahuatanga PIN i raro nei he raarangi whanui mo nga titi katoa pea mo nga waahanga DDR3 katoa. Nga titi katoa kua tohua kaua e tautokohia i runga i tenei waahanga. Tirohia nga tohu PIN mo nga korero mo tenei waahanga.
Hoahoa poraka poraka
4GB, 512mx64 kōwae (2Rank o X8)
Te inenga kōwae
Tiro o mua
Tiro o mua
Nga tuhinga:
1.A nga rahinga kei roto i nga millimeters (inihi); Max / min ormmalical (typ) te wahi i tuhia ai.
2.Telence i runga i nga waahanga katoa ± 0.15mm mena kaore i tohua.
3.Ko te hoahoa ingoa mo te tohutoro anake.
Ngā Hua Hua : Taonga Taputapu Matapihi Ahuwhenua
Tauākī Tūmataitinga: He mea tino nui to maatauranga ki a matou. He kupu nui to maatau kamupene kia kaua e whakaatu i o korero whaiaro ki tetahi atu whakaaetanga.
Whakakiia etahi atu korero kia taea ai e koe te pa ki a koe kia tere ake
Tauākī Tūmataitinga: He mea tino nui to maatauranga ki a matou. He kupu nui to maatau kamupene kia kaua e whakaatu i o korero whaiaro ki tetahi atu whakaaetanga.